The voltage integrator is an ordinary circuit, implemented for instance in filter structures using the CMOS technique. This is demonstrated by a prior art circuit shown in FIG. 1a, being conventionally implemented by means of an operational amplifier. FIG. 1b shows an alternative implementation of the state of the art based on the use of capacitors switched in discrete time. The output signal Uo of the integrator shown in FIG. 1a is the time integral of the input voltage Ui derived according to the following formula: EQU Uo(t) = - (1/RC) .sub.o .intg..sup.t Ui(t) dt
Similarly, the output signal Uo of the integrator shown in FIG. 1b is formed by formula EQU Uo(t) = fs (Ci/Co) .sub.o .intg..sup.t Ui(t) dt
where fs is the sampling frequency. In the sampling capacitor Ci a charge sample of the input signal is stored when the switches s1 and s4 are closed and the switches s2 and s3 are open. The sample charge (Qi = Ci .times. Ui) is discharged in the integrating capacitor Co by closing the switches s2 and s3, and the switches s1 and s4 are now open. There may be pauses between the sample storing and sample discharge stages when all four switches s1 to s4 are open.
A drawback related to state of art the circuits is that the amplifier continuously consumer current, this being of an order of magnitude from 50 .mu.A to several 100 .mu.A. Moreover, the amplifier contains a limited bandwidth which is in general proportional to the current consumption, and in a CMOS implementation, harmful 1/f noise. The function of amplifiers such as those shown in FIG. 2 is to transfer a signal charge taken in the sampling capacitor Ci into the integrating capacitor Co. This is implemented when the gain of the amplifier is infinite (in practice thousands or even millions), for which purpose a continuous current flows in the amplifier.
The publication DE-29 33 667 shows a lossy integrator, not consuming static current and corresponding to a passive RC integrator. With such an integrator, merely passive transfer function (i.e., those located on the real axis) can be implemented so that the design disclosed in DE-29 33 667 is not an appropriate element for filters in the transfer function of which complex poles are contained. In publications DE-29 33 667, U.S. Pat. No. 5,021,692, and N. C. Battersby, C. Toumazou: A new generation of class AB switched-current memory for analog sampled-data applications, Proc. ISCAS 1991, designs are disclosed based on current-mode signal processing in which the static current consumption is low. However, each circuit requires a so-called bias-current. For example, U.S. Pat. No. 5,051,692 discloses an integrated circuit provided with a sampling capacitor, which is connected via an active element to be in conductive connection with the supply voltage and which is provided with an integrating capacitor for producing an output signal, but said circuit requires a continuous bias current. Also in publications J. B. Hughes, N. C. Bird, I. C. Macbeth: Switched currents, a new technique for analog sampled data signal processing, Proc. ISCAS 1989 and T. S. Fief, D. J. Allstot: CMOS switched current ladder filters, IEEE JSSC Vol 25 No 6 (Dec 90) illustrate the state of the art is illustrated. Thus, only in Finnish Patent No. 89,838 (corresponding U.S. Pat. No. 5,387,874 and publication EP-473436), has it been possible to eliminate the static current consumption entirely, which feature will be described below for a greater understanding of the present invention.
U.S. Pat. No. 5,387,874 discloses an integration method in which the current consumption is zero. This is reached by using one or two transistors as an active member to control both the taking of a charge sample and transferring it to an integrating capacitor. The other switches required in the operation of the circuit are executed and they are used in a manner known in itself in the art. In the circuit described therein no active continuous-operated amplifier is needed, instead, the transfer of a charge from the sample capacitance to the integrating capacitance is controlled with switching elements, switching one of the sample capacitance terminals to either the positive or the negative supply voltage. At the conclusion of charge transfer, the passage of current totally ends so that the continuous current consumption is eliminated.
According to a preferred embodiment, the integrating capacitance is procharged by connecting it to the positive or negative supply voltage for storing the sample charge.
The method according to U.S. Pat. No. 5,387,874 includes advantageously two charge sample discharging stages, whereby at the first stage a charge sample is conducted to an integrating capacitance only if it has a first sign, i.e. polarity, (e.g. positive or negative), and whereby at the next stage a charge sample is conducted to the integrating capacitance only if it has the opposite sign (polarity, e.g. negative or positive), whereby the first sign has been proselected. The sign of the charge of the sample capacitance can be identified with a comparative circuit member, whereby, depending on the identified sign, only one of the two charge sample discharging stages is carried out.
In an embodiment according to U.S. Pat. No. 5,387,874, a transistor is used as the switching element for discharging a sample charge. In said embodiment, the switching element switching the sampling capacitance to the supply voltage is a bipolar transistor. In an alternative embodiment the switching element is a FET transistor.
In a most preferred embodiment, the switching element is an EPROM-type FET transistor, the floating gate thereof having been arranged to carry a predetermined charge so that the threshold voltage of the FET transistor is of a desired magnitude, most preferably substantially zero. Hereby, the circuit operates almost ideally because e.g., no compensation of the threshold voltages occurring in bipolar transistors is required.
The basic design of the circuit not consuming the static current and of the method, presented in U.S. Pat. No. 5,387,874 is described below more in detail with the aid of embodiment examples, reference being made to the accompanying drawings, in which: